NVIDIA Blackwell, new Google TPUs, and hyperscaler ASICs defined who trains and infers at what cost.
NVIDIA’s Blackwell roadmap and TPU/Trainium/Inferentia generations sustained compute supply. Scarcity and export controls still shaped geopolitics.
Firms designed kernels and “shape-aware” models for hardware. Software is co-designed with the chip.
Without this layer, 2025–2026 frontier-model announcements would not exist: AI history is also fab history.
New accelerators promise up to 4× better energy efficiency for LLM inference.
Per an internal memo reviewed by Reuters in July 2026, Meta planned to begin manufacturing its Iris accelerator from September within a four-generation MTIA program, with Broadcom on design and TSMC on fabrication. September coverage indicates production has started; infrastructure ambition is ~7 GW in 2026 and double (14 GW) in 2027, supplementing—not replacing—Nvidia and AMD GPUs.
On September 14, 2026, Forbes and RuntimeWire covered Cognichip’s enterprise launch of Artificial Chip Intelligence (ACI), founded by Faraj Aalaei. The system uses native physics-informed models—not LLM wrappers—for microarchitecture, RTL, verification and PPA; one cited case compressed a 55-page spec into days versus 4–5 months. Public evidence remains company and customer benchmarks.